Gallium-arsenide based field-effect transistors utilizing the depletion region formed by a metal-semiconductor junction, commonly known as Schottky junction, to modulate the conductivity of an underlying channel layer have gained acceptance as a high performance transistor technology owing to inherent physical properties of the gallium arsenide and related ternaries indium gallium arsenide. Such devices are referred to by those of ordinary skill in the art by various names such as metal semiconductor feild effect transistors (MESFET), high electron mobility transistors (HEMT), psuedomorphic high electron mobility transistor (pHEMT), two dimensional electron gas field effect transistors (TEGFET) and modulation doped field effect transistors (MODFET). Further details of the dynamics of charge transport in these structures can be found in Quantum Semiconductor Structures by Weisbuch, et al., 1991 by Academic Press, pages 38-55 and pages 141-154, the disclosure of which is specifically incorporated herein by reference.
In field effect transistors (FET) the current between the source and drain contacts is controlled by a potential applied to the gate electrode. The function of the device is relatively basic. In logic circuits the devices often function as switches, by virtue of the fact that the gate voltage can act as a valve in turning off current between the source and the drain in a region well-known as the channel. In analog circuits, small time-varying voltage on the gate results in a time varying current between the source and the drain, and because the gate current is ideally a pure displacement current, a very small input power can be readily amplified.
The basic gallium arsenide metal semiconductor field effect transistor known as a MESFET has the source and drain current carried via a relatively thin, highly doped, semi-conductor layer, the channel. The current is controlled by the gate which forms a Schottky barrier on the semiconductor, and therefore depending upon the applied gate voltage depletes the semiconductor layer of electrons under the gate. Other devices enumerated above to include the HEMT, pHEMT, and MODFET are based on the basic principles described above. The structure of a basic HEMT is based on the heterojunction between two dissimilar materials, AlGaAs (Aluminum Gallium Arsenide) and GaAs (Gallium Arsenide) well-known to one of ordinary skill in the art. The essential structure consists of a semi-insulating substrate on which is first grown a buffer layer of nominally unintentionally doped GaAs. An n-doped layer of gallium arsenide, or pseudomorphic indium gallium arsenide, forms the channel for the device. An n.sup.- layer of Al.sub.x Ga.sub.1-x As is disposed on top of the channel layer to form a proper Schottky barrier with the gate metalization. The last layer is typically a GaAs contact layer which is doped highly n-type to facilitate the formation of ohmic contacts to the underlying channel layer. The two ohmic contacts disposed on this layer are generally referred to as the source and drain contacts. Access resistances associated with these contacts and the underlying semiconductor material to the intrinsic device are typically referred to as R.sub.s and R.sub.d, the source and drain resistances, respectively.
In analog applications, there are a several factors which are of prime importance. To this end, gain, noise, and total microwave output power are factors which are of prime consideration in the design of GaAs based field effect transistors. The transconductance, or gain, for an FET device is defined as the follows: EQU g.sub.m =dI.sub.ds /dVg
where I.sub.ds is the current between the drain and source, Vg is the gate voltage. Further, gm can be estimated for a high-low-high MESFET with relatively thin channel layers for example by the following expression EQU g.sub.m=.epsilon.V.sub.sat w.sub.g /t
where .epsilon. is the permtivity of GaAs, V.sub.sat is the saturation velocity of electrons in GaAs, w.sub.g is the width of the gate electrode, and t is the gate electrode to channel spacing. For further details, see for example J. L. Walker, High-Power GaAs FET Amplifiers, Artech House, Boston, pp 50-56, the disclosure of which is specifically incorporated herein by reference. To first order, the speed of operation of the device makes it necessary to reduce as much as practically possible the gate length and to find structures and materials which have high average velocity of carriers under the gate. Another observation can be made from the above equation: as the layer of n.sup.- material under the gate metalization is made thinner, the gain is greater. From a simple perspective of electrostatics, the thinner the n.sup.- layer between the channel and the gate metalization is, the greater the influence of the electric field on the channel conductivity through depletion of carriers. Accordingly, by making this layer thin, for a given change in the gate voltage, a greater control is realized over carriers in the channel, and therefore a greater change in I.sub.ds is realized. Thus, the transconductance is greater. Additionally, the closer the gate metalization is to the channel, the lower is the pinch off voltage, or the voltage required to reduce the drain current to a negligible value.
Therefore, in brief summary, the GaAs FET structure of devices of the present disclosure functions by applying a potential to the gate to modulate to conductivity of the underlying channel and thereby to control the source-to-drain current which results from a positive potential applied from drain-to-source. The preferred structure of a highly doped channel (n), a lightly doped (n.sup.-) Schottky layer and a highly doped n.sup.+ contacting layer is known as a high-low-high structure. A material should be chosen to improve the velocity of carriers in a channel, so as to improve the gain of the device by the equation set forth above.
It is common that the manufacture of FET devices entails techniques to fabricate devices having performance characteristics of saturated drain-to-source current, transconductance, and pinch off voltage which are within tolerance require an iterative, single wafer-recess etch process. Such a recess etch is used to increase the transconductance of the device while simultaneously improving the breakdown voltage of the transistor as described in J. L. Walker, High-Power GaAs FET Amplifiers, Artech House, Boston, pp 66-72, the disclosure of which is specifically incorporated herein by reference. Specifically, proper etch depth is attained by etching a wafer, measuring the source-to-drain current, and repeating this procedure until a target value is attained. To this end, the contact layers on which the drain and source metalizations are disposed are etched down and reveal the n.sup.- layer which provides the surface on which the gate electrode is subsequently disposed. This iterative procedure is labor intensive requiring a technician to measure drain-to-source current following each itteration of etch to determine if the target current has been attained. This very labor intensive process is often not reproducible in reliable manner. In addition, a certain point will be reached in the etching process where the source-to-drain current reaches an unacceptable value. This condition is referred to as overetch and results in devices which do not meet performance specifications. Additionally, such iterative processing often results in etch depth variation across the wafer and from wafer-to-wafer. This dimensional variation has a direct impact on the performance variation. For example, a 5% across-wafer variation in pinchoff voltage is often realized. The variation of this parameter across the process can typically exceed 12%. Parameter variation is defined here as standard deviation divided by average.
The use of selective chemistry to stop the recess etching process at a depth determined by the placement of the stop layer has been shown to improve the uniformity and reproducibility of the depth. The benefit of such a device is that one can control the gate-to-channel spacing to a desired level limited only by the uniformity of the process used to form the epitaxial layers. Additionally, the significant labor input can be reduced from the etch procedure as the recess etch can be performed in batch. Previous techniques to provide an etch stop have been done with materials such as AlAs, or more specifically Al.sub.x Ga.sub.1-x As. One such technique is disclosed in U.S. Pat. No. 5,374,328 to Remba, et al., the disclosure of which is specifically incorporated by reference herein. Unfortunately, the use of such materials can have deleterious effects on devices through an increase in the device access resistances. As stated previously, access resistance is a general term used to describe what are commonly referred to in the art as the source and drain resistances. An increase in the device source resistance, for example, reduces the extrinsic transconductance of the device as described by the following relation found in many texts on semiconductor device physics (see for example S. M. Sze, Physics of Semiconductor Devices, John Whiley and Sons, New York, 1969, p. 355 the disclosure of which is specifically incorporated herein by reference) EQU g.sub.me =g.sub.mi /(1+g.sub.mi R.sub.s),
where g.sub.me is the extrinsic transconductance of the device as measured at its external terminals; g.sub.mi is the intrinsic transconductance or that which the device would exhibit if the source resistance were negligible; and R.sub.s is the source resistance of the device. Further, an increase in the device access resistances will increase the drain-to-source voltage at which the drain current saturates what is often referred to in the art as the knee voltage. The increased knee voltage can limit the power performance of the device. The access resistances are often described as being comprised of two primary elements, one associated with the metal-semiconductor interface, the other associated with the semiconductor material outside of the influence of the gate electrode. The insertion of an etch-stop layer into the structure adds an additional resistive component to the device access resistances. This component is associate with a tunneling barrier imposed by the offset in the minimum allowed energies of conduction electrons between the two dissimilar materials often referred to in the art as conduction band discontinuity. The greater the conduction band discontinuity, the greater the associated resistance. Reported experimental values of the conduction band discontinuity, that for the AlAs/Gas materials system is on the order of 500 meV.
Accordingly, what is needed is a device which has the improvements in device manufacturablilty which can be effected by a suitable etch-stop material while not suffering the drawbacks of increased access resistances experienced with conventional etch-stop materials.